The present disclosure relates to a semiconductor structure and a method of forming the same. More particularly, the present disclosure relates to semiconductor structures including vertical transistor structures employing deep trenches which may be used in memory devices such as, e.g., embedded dynamic random access memory (eDRAM) in order to enhance device density and mitigate deficiencies associated with shorting and lateral overgrowth issues, including lateral eDRAM to eDRAM shorts.
DRAM employs memory cells usually having a transistor and a storage capacitor embedded in a deep trench and arranged in series. eDRAM embeds these memory cells into the same semiconducting material that contains a microprocessor, which allows for wider buses and faster operating speeds (as compared to DRAM) in an integrated circuit (IC) chip. Many of these embedded memory cells, including transistors and storage capacitors, can be arranged on a single chip or within a single package to define an array. Operation of the memory cells is controlled by various circuits, many of which are structurally different from each other and warrant different manufacturing techniques.
Conventional vertical transistors are devices where the source-drain current flows in a direction normal to the substrate surface. In such devices, a vertical semiconductor pillar defines the channel with the source and drain located at opposing ends of the semiconductor pillar. One advantage of a vertical transistor is that the channel length is not defined by lithography, but by methods such as epitaxy or layer deposition, which enable precise dimensional control.
As such, vertical transistors are an attractive option for technology scaling to smaller nodes, but the increasing density in those technology nodes introduces various adverse effects that require attention to improve device performance.